Nehalem Part 3: The Cache Debate, LGA-1156 and the 32nm Future
by Anand Lal Shimpi on November 19, 2008 8:00 PM EST- Posted in
- CPUs
Mainstream Nehalem: On-chip GPU and On-chip PCIe
Let’s take a look at the Core i7, the first Nehalem incarnation:
Three DDR3 memory channels, a QPI link to the X58 chipset and support for multiple GPUs off of the X58 IOH. The Core i7, as you know by now, plugs into Intel’s new LGA-1366 socket. But in the second half of next year, there will be a new socket for mainstream users: LGA-1156.
Meet Lynnfield, it’s also a 4-core/8-thread design with an 8MB L3 cache, just like the Core i7, but it plugs into LGA-1156. Instead of 3-DDR3 channels it’s got two and instead of QPI it’s got Intel’s DMI connecting it to the chipset. It’s a lower bandwidth interconnect but Lynnfield doesn’t need a ton of bandwidth between it and the chipset, the reason being its secret weapon: Lynnfield has an on-package PCIe controller.
There are 16 PCIe lanes on Lynnfield (presumably PCIe 2.0) and they can be used as two x8s or a single x16, so you’ll get 2-way SLI/CrossFire support assuming all licensing silliness is worked out. The close proximity of the PCIe controller to the CPU could mean some very interesting things for latency, if well designed Lynnfield could have the lowest latency CPU-GPU connection we’ve seen on a desktop PC. Whether or not that’ll actually mean anything for real world performance remains to be seen, I’d guess not but it’s neat to talk about nonetheless.
Next up we’ve got Havendale, this is a 2-core/4-thread part with a 4MB L3 (still 2MB of L3 per core, just like Lynnfield and the Core i7). The “pinout” (if we can still call it that on these pinless CPUs) is the same as Lynnfield, so we’ve got a two channel DDR3 memory controller and DMI to the chipset.
Havendale’s secret sauce is that it’s got an on-package GPU, I’d expect it to be a bigger, better, faster variant of G45 (hopefully a lot better/faster) built on a 45nm process. This should beat AMD to the punch with the first single-chip CPU/GPU for mainstream desktops/notebooks, as AMD delayed its first APUs until 2011. Alongside the on-package GPU we've also got the same PCIe controller from Lynnfield.
The actual display output on Havendale will be through the chipset itself but the GPU and PCIe interface are on the CPU’s package. Harvendale only offers a single x16 PCIe slot, you can’t run it in 2 x8 mode.
At the right clock speeds, Havendale should be perfect for notebooks and desktops as well. These days two-cores with Hyper Threading would be the perfect mixture of cores/performance for the majority of consumers. As I noted in part 2 of our Nehalem coverage, give me Nehalem’s power efficiency in a notebook and I’ll be beyond happy.
The hiccup however is that we won’t see Havendale until Q1 2010. It’ll start production in Q4’09 but systems won’t ship until the beginning of the next year. This does leave a hole in Intel’s Nehalem roadmap as there won’t be any Intel integrated graphics chipsets between now and Q1 2010, which should give NVIDIA ample opportunity to sell chipsets into the mainstream Nehalem market.
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SiliconDoc - Saturday, December 27, 2008 - link
" The move to multi-core chip designs meant that the focus was no longer on feeding the individual core, but making sure all of the cores on the chip were taken care of. It’s all so very socialist (oh no! ;) ). "Umm... wouldn't socialist be more like feeding one or two of the four cores, and all you get back is cache misses, or a stalled pipeline anyway ? I mean, if you're feeding the core, it is expected to do some work. So this is clearly not socialist.
Maybe you meant it's socialist in the sense that all 4 cores can't be kept fed and therefore working, so most the time they're standing around with the shovel, because yeah they are "on the job", but they ain't doing much, but the clock keeps ticking and ticking... gosh when is the city street core gonna move that and+ sign, and why does it take 5cas to get it done...look at that the bueaucratic core keeps pushing through dirty bits paper and asking for another copy...
:-0)
Yes, making the 256k cache work properly to "feed" all the cores and keep them working is the exact opposite of socialism. The exact opposite.
JonnyDough - Friday, November 21, 2008 - link
I think it's pretty obvious what's happening here. Intel is pedaling slowly, waiting for AMD to catch up. It's obvious to everyone that more cache would feed the cores better, but with nothing from AMD to answer - there's no need to make huge gains. They'd prefer to milk the market with incremental advances and sell us the same architecture more times, increasing cache as they will.Bullfrog2099 - Friday, November 21, 2008 - link
Theres one more thing that Intel needs to be grilled about.Will Bloomsfield and Westmere run on the same motherboard since they both use the same socket? Or will you have to buy a new mb if you want to upgrade to 32nm?
USSSkipjack - Thursday, November 20, 2008 - link
I am also very concerned about the cache sizes in the Nehalem architecture. We are doing interactive realtime software volume rendering and that has naturally a very high demand on the CPU. A current Q9450 is actually doing quite well due to its large cache (12 MB) it is also quite inexpensive for its power. Actually we need pure FP power and the ability to feed large amounts of data to the CPU in a short time. Just imagine gigabytes of data that need to be processed in realtime.Of course faster is always better and due to the nature of our renderer it also scales very nicely with additional cores. So we were hoping for the release of an affordable 8 core (single package or die) product before the first quarter of next year. Instead we get Nehalem which seems to be inferior for our cause due to its smaller (and slower) cache. Hyperthreading wont help us much, due to the FP nature of almost everything we do.
Still I am somewhat encouraged by the rather good benchmarks we have seen so far. So my question is, in a direct comparison how does a very cache dependent application do in a Nehalem CPU versus a Q9750 or simillar current quad core?
Anyone got any benchmarks that shed light on that?
bollux78 - Thursday, November 20, 2008 - link
MAY BE with current knowledge (or lack of) about general physics and stuff that overcome any industrial attempt, there is nothing very exciting to do about processors. We REALLY should stop thinking stuff will go faster and faster and start to look back at real programmers that made miracles on insignificant hardware, like the amiga, lots of jap PCs etc. Video games should not be even commented, because their hardware is un-upgradeable, and yet, the guys make things run on them no matter what. see PS2 as an outrageous example. they made all NFS series on n and more, and nobody put more than 32mb of ram. I´m sorry guys (ans gals where applicable) but this is all bull, people wanting to tease all of us with new unncessary hardware, lots of useless modifications that make no sense for the end user etc. There should be more programmers and soft engineers and less wall street bastards.mutarasector - Monday, November 24, 2008 - link
"We REALLY should stop thinking stuff will go faster and faster and start to look back at real programmers that made miracles on insignificant hardware, like the amiga, lots of jap PCs etc."As a former Amiga software developer, I tend to agree with this statement. While I wouldn't go quite so far as to say we shouldn't expect to see hardware speed improvements, I would modify that expectation in that future hardware R&D shouldn't be oriented towards 'brute force' speed enhancements, but should be more granular refinements. To be sure, I think we are indeed seeing this from both AMD and Intel, particularly with cache structuring and power optimizations.
The *real* problem here is that hardware development is still largely driven by an agenda with an eye towards favoring Microsoft bloatware on monolithic architectures by AMD and Intel. This is ultimately a dead-end as it still fails to address the fundamental mindset changes required to push computing technologies forward in the long term. The first (and most important) change is to get OS and application development moving towards more tightly handcrafted/refined coding that assumes more responsibility for things currently implemented in silicon rather than contiuing down the path of "how can continue to take it up the whazoo endlessly refining our silicon to satisfy Microsoft bloatware requirements".
Microsoft and Google are racing towards iOS dominance (even though
at times I think M$ forgets this race is even on), but of the two, Google is clearly the leader here. What would be cool is if Google would get guys like Carl Sassenrath (Amiga Exec/OS developer) to glue it's Google apps together on Carl's REBOL platform.
Shmak - Friday, November 21, 2008 - link
While I follow your reasoning with newer, better, faster, and smaller being crammed down our throats, but speed issues cannot be resolved as easily through the software side of things. The software industry has come to rely on the current cycle of ever speedier hardware.And rightfully so, as nobody wants to have to translate millions of lines of C into Assembler for better efficiency than compliers do. Not to mention the fact that every piece of software with a decent budget uses 3rd party platforms like Direct X. Sure somebody could probably write something more efficient for the specific aims of their game or whatever, but it would probably take them far longer than just integrating the platform as is. Not to mention the fact that many of these things are like "black boxes" that have to be opened up and figured out in order to be improved upon, and people generally don't like messing with code that isn't their own. Yet these 3rd party bits are necessary in the end.
The final thing is that when you program anything decent sized for a PC, you are depending on other people's code. The drivers, the OS, Open CL, whatever, all these things make it possible for consumers to use a variety of hardware. Game consoles and the Amiga could be fine tuned because the developers knew the machine they were testing on was EXACTLY the same as the one that was sitting in your office/living room however many years ago.
USSSkipjack - Thursday, November 20, 2008 - link
Yes, but... physics also limit the amount of data that a current CPU can process either way you see it. One can of course fake things, but there are applications (like ours) where this is not an option. Faking and smoke and mirrors and optimizations are something that works very well for games and even for movie effects work, but we can not do that.It is already a miracle that we do the stuff we do with the current hardware (most others try to use GPUs or even expensive special purpose hardware for that, with all the issues that come with this).
The advantage of using the CPU is scalability. We do fine on a current Q9450, now imagine what we can do on two?
My issue is whether we should do that, or whether Nehalem will indeed bring benefits even for us, even it has a smaller cache. Maybe the new cache configuration and the architecture outdo the lack of cache. This is why I would like to see a direct comparison of Nehalem CPU with a Q9750 in apps that are particularily benefited by larger caches and/or that process a lot of data.
Also, does anyone know when the 8-core Nehalems will come to market?
chizow - Thursday, November 20, 2008 - link
Glad you grilled them about Nehalem's lack of L2 Anand. Lots of good info there, but you should've asked him point-blank if he knew Nehalem didn't show any improvement and in many cases, was slower than Penryn in games. It would've been interesting to hear Ronak's response to that. There's the Guru3D article that shows significant gains in Tri-SLI with an i7 but I haven't seen any other reviews that show nearly as much gain. Hopefully the L3 latency tweaks in Westmere improve gaming performance, but for now there doesn't seem to be much reason for gamers to upgrade from Core 2.ltcommanderdata - Thursday, November 20, 2008 - link
Does having a L3 cache inherently impose a latency constraint on the L2 cache? Afterall, the last time Intel had an independent L2 cache it was on Dothan which was 2MB with 10 cycle latency. Now Nehalem's independent L2 cache is only 256k at 10 cycles and they say going to 512k would have made it 12 cycle.So Westmere is really just going to be a die shrink? I was hoping it'll be something like Penryn, which even though it didn't change that much, I believe it still outperformed Conroe by 5-10% on average. I believe there are some more SSE instructions coming for Westmere for AES and other things.
Supposedly the OpenCL spec has been completed in record time thanks to pressure from Apple to get it out in time for Snow Leopard. It's only awaiting lawyer IP approval. Any chance of getting the details?