Overclocking Intel's New 45nm QX9650: The Rules Have Changed
by Kris Boughton on December 19, 2007 2:00 AM EST- Posted in
- CPUs
Exploring the Limits of 45nm Silicon
During the course of our testing we made a rather interesting discovery regarding 45nm silicon scaling: a window exists in which CPU frequency responds in a highly proportional manner. Calculating this value later tells us that between 3.0GHz and 4.0GHz our processor requires ~0.3mV (0.0003V) more Vcore for each one megahertz increase in core frequency. Since our QX9650 is capable of running the stock 3.0GHz setting at only 0.98V, this means that achieving a stable 3.6GHz overclock requires 0.98V + (0.3mV/MHz)(600MHz) = 1.16V. This general trend continues all the way to about 4.0GHz where we found total stability at an amazingly low 1.28V. We cannot help but feel excited about Intel's new 45nm process, especially considering such early maturity.
Always target the higher end of the Proportional Overclocking Region
Dropping below 3.0GHz allows us a chance to experiment in the world of low-voltage (LV) and ultra low-voltage (ULV) clocking. Two point four gigahertz (2.4GHz) was possible at only 0.90V. Additionally, the lowest possible core speed that we could dial-in using the ASUS P5E3 (6 x 200MHz = 1.20GHz) had no problems maintaining stability at only 0.81V. It's interesting to note that this is also the lowest Vcore we could supply the CPU, as VID settings below 0.85000 were not available for use. As an aside, the VRM 11.0 specification, used extensively by motherboards supporting 65nm CPUs, calls for selection values down to 0.70000V.
As expected, pushing the QX9650 above 4.0GHz, although possible, also demands more Vcore than predicted by our simple scaling equation. In fact, running well in excess of this speed requires a nearly exponential increase in voltage. At this point gains are small and generally not worth the extra heat produced because of the excess power consumed. Clearly, the more efficient silicon switching that comes with better cooling is needed if we planning to go much higher. Oddly enough, for the first time in water-cooled quad-core history, we feel as though heat is not the limiting factor. Rather than push this finding aside, we decided to examine the cause a little more closely.
We start our investigation by comparing our measured processor power consumption values with those found through use of the well-known power scaling equation (shown above). The equation wonderfully predicts what we see at lower frequencies but quickly falls behind actual measured values when looking at higher speeds:
A quick check for clues as to the differences turns up one important oversight. Intel's newest power prediction equation includes an extra factor - processor capacitance. Research indicates that the capacitance associated with the transistors gates has become quite significant; possibly more so with 45nm Hi-k transistors than those made using any other previous process technology. We decided to establish the region boundary in the plot above using the point in which this effect became significant, even though the extra transistor capacitance created at higher switching frequencies begins to manifest itself as additional power required at lower processor speeds (around 3.6GHz). At 4.0GHz this additional factor accounts for 25% more power than would otherwise be predicted.
Although we cannot explain exactly why capacitance becomes such a large factor at higher speeds, average core temperature may be a factor. This would certainly help to explain why microprocessors experience such dramatic increases in switching efficiencies when super cooled. Typically, a processor needs significantly less voltage in order to run equivalent speeds under phase-change or liquid nitrogen than would be required with typical air or water-cooling. In fact, based on what we have seen, these 45nm processors may be the first of many in which overclockers find they reach silicon limits before anything else. In the past, it was comforting to know that a bigger heatsink, more powerful fan, or a better water block held the promise of a higher overclock; with 45nm this may no longer be the case.
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Lifted - Wednesday, December 19, 2007 - link
Very impressive. Seems more like a thesis paper than a typical tech site article. While the content on AT is of a higher quality than the rest of the sites out there, I think the other authors, founder included, could learn a thing or two from an article like this. Less commentary/controversy and more quality is the way to go.AssBall - Wednesday, December 19, 2007 - link
Shouldn't page 3's title be "Exlporing the limits of 45nm Halfnium"? :Dhttp://www.webelements.com/webelements/elements/te...">http://www.webelements.com/webelements/elements/te...
lifeguard1999 - Wednesday, December 19, 2007 - link
"Do they worry more about the $5000-$10000 per month (or more) spent on the employee using a workstation, or the $10-$30 spent on the power for the workstation? The greater concern is often whether or not a given location has the capacity to power the workstations, not how much the power will cost."For High Performance Computers (HPC a.k.a. supercomputers) every little bit helps. We are not only concerned about the power from the CPU, but also the power from the little 5 Watt Ethernet port that goes unused, but consumes power. When you are talking about HPC systems, they now scale into the tens-of-thousands of CPUs. That 5 Watt Ethernet port is now a 50 KWatt problem just from the additional power required. That Problem now has to be cooled as well. More cooling requires more power. Now can your infrastructure handle the power and cooling load, or does it need to be upgraded?
This is somewhat of a straw-man argument since most (but not all) HPC vendors know about the problem. Most HPC vendors do not include items on their systems that are not used. They know that if they want to stay in the race with their competitors that they have to meet or exceed performance benchmarks. Those performance benchmarks not only include how fast it can execute software, but also how much power and cooling and (can you guess it?) noise.
In 2005, we started looking at what it would take to house our 2009 HPC system. In 2007, we started upgrades to be able to handle the power and cooling needed. The local power company loves us, even though they have to increase their power substation.
Thought for the day:
How many car batteries does it take to make a UPS for a HPC system with tens-of-thousands of CPUs?
CobraT1 - Wednesday, December 19, 2007 - link
"Thought for the day:How many car batteries does it take to make a UPS for a HPC system with tens-of-thousands of CPUs?"
0.
Car batteries are not used in neither static nor rotary UPS's.
tronicson - Wednesday, December 19, 2007 - link
this is a great article - very technical, will have to read it step by step to get it all ;-)but i have one question that remains for me.. how is it about electromigration with the very filigran 45nm structures? we have here new materials like the hafnium based high-k dielectricum, guess this may improove the resistance agains em... but how far may we really push this cpu until we risk very short life and destruction? intel gives a headroom until max 1.3625V .. well what can i risk to give with a good waterchill? how far can i go?
i mean feeding a 45nm core p.ex. 1,5V is the same as giving a 65nm 1,6375! would you do that to your Q6600?
eilersr - Wednesday, December 19, 2007 - link
Electromigration is an effect usually seen in the interconnect, not in the gate stack. It occurs when a wire (or material) has a high enough current density that the atoms actually move, leading to an open circuit, or in some cases, a short.To address your questions:
1. The high-k dielectric in the gate stack has no effect on the resistance of the interconnect
2. The finer features of wires on a 45nm process do have a lower threshold to electromigration effects, ie smaller wires have a lower current density they can tolerate before breaking.
3. The effects of electromigration are fairly well understood at this point, there are all kinds of automated checks built in to the design tools before tapeout as well as very robust reliability tests performed on the chips prior to volume production to catch these types of reliability issues.
4. The voltage a chip can tolerate is limited by a number of factors. Ignoring breakdown voltages and other effects limited by the physics of transistor operation, heat is where most OC'ers are concerned. As power dissipation is most crudely though of in terms of CVf^2 (capacitance times voltage times frequency-squared), the reduced capacitance in the gate due to the high-k dielectric does dramatically lower power power dissipation, and is well cited. The other main component in modern CPU's is the leakage, which again is helped by the high-k dielectric. So you should expect to be able to hit a bit higher voltage before hitting a thermal envelope limitation. However, the actual voltage it can tolerate is going to depend on the CPU and what corner of the process it came from. In all, there's no general guideline for what is "safe". Of course, anything over the recommended isn't "safe", but the only way you'll find out, unfortunately, is trial and error.
eilersr - Wednesday, December 19, 2007 - link
Doh! Just noticed my own mistake:high-k dielectric does not reduce capacitance! Quite the contrary, a high-k dielectric will have higher capacitance if the thickness is kept constant. Don't know what I was thinking.
Regardless, the capacitance of the gate stack is a factor, as the article mentioned. I don't know how the cap of Intel's 45nm gate compares with that of their 65nm gate, but I would venture it is lower:
1. The area of the FET's is smaller, so less W*L parallel plate cap.
2. The thickness of the dielectric was increased. Usually this decreases cap, but the addition of high-k counter acts that. Hard to say what balance was actually achieved.
This is just a guess, only the process engineers no for sure :)
kjboughton - Wednesday, December 19, 2007 - link
Asking how much voltage can be safetly applied to a (45nm) CPU is a lot like asking which story of a building can you jump from without the risk of breaking both legs on the landing. There's inherent risk in exceeding the manufacturer's specification at all and if you asked Intel what they thought I know exactly what they would say -- 1.3625V (or whatever the maximum rated VID value is). The fact of the matter is that choices like these can only be made by you. Personally, I feel exceeding about 1.4V with a quad 45nm CPU is a lot like beating your head against a wall, especially if your main concern is stability. My recommendation is that you stay below this value, assuming you have adequate cooling and can keep your core temperatures in check.renard01 - Wednesday, December 19, 2007 - link
I just wanted to tell you that I am impressed by your article! Deep and practical at the same time.Go on like this.
This is an impressive CPU!!
regards,
Alexander
defter - Wednesday, December 19, 2007 - link
People stop posting silly comments like: "Intel's TDP is below real power consumption, it isn't comparable to AMD's TDP".Here we have a 130W TDP CPU consuming 54W under load.