A New SSE Instruction Set: AMD Announces SSE5
by Ryan Smith on August 30, 2007 4:00 PM EST- Posted in
- CPUs
While extending the x86 instruction set with new iterations of SSE has become a regular activity in the computing industry, many of these additions are in actuality a gradual reshaping of x86 processors. Although as a general purpose CPU design x86 doesn't have any hard limitations (given enough time you can do any kind of calculation required) it has had several weak points patched up over the years. The basis of identifying and patching these weak points has been looking at what processors - general and specialized - are doing well while x86 is doing poorly at the time. Each iteration of SSE so far has then implemented features that these other processors have to erase these weak points.
All told, SSE5 includes 46 unique "base" instructions, with many of those instructions featuring several variations that work on different data types. With all of these variations, the total number of instructions introduced altogether with SSE5 is 170. For comparison's sake, the entire original x86 instruction set was a mere 80 instructions.
With SSE5, AMD is focusing on 5 groups of instructions. Those groups are:
- Fused multiply accumulate (FMACxx) instructions
- Integer multiply accumulate (IMAC, IMADC) instructions
- Permutation and conditional move instructions
- Vector compare and test instructions
- Precision control, rounding, and conversion instructions
As we hinted to earlier, many of these instructions are implementations of features found elsewhere. DSPs in particular have been and continue to be a major source of new instructions for new versions of SSE, with many of these instructions allowing for a CPU to process data for specialized cases at DSP-like speeds.
Additionally, AMD has taken a particular interest in the weakness of the very core of x86, which is how the instructions are formed and handled. A single binary-form instruction for an x86 processor (or most other processors for that matter) is a combination of two parts: an opcode and operands. The opcode is the segment of the instruction that says what to do, the operands are the data elements that will be operated upon and any further specifiers the processor needs to execute the instruction. As far as the x86 instruction set is concerned, this is normally very cut & dry: 2 bytes for the opcode, and then the rest of the instruction is the operands, with the vast majority of instructions using between 0 and 2 data element operands.
AMD is making changes to both the opcode and operand design as part of SSE5, with the latter in particular intended to make many of the new performance-improving instructions possible. For the opcode, AMD is adding a third byte to the opcode - this is necessary to provide the bits needed to identify the new instructions, and provide some controls over the use of the new operand features. As for the operand, SSE5 includes numerous instructions that require the use of more than 2 data element operands; the format of the operands is not so much the point here as is the potential power of having additional operands. One way to improve performance is to operate on more pieces of data in a given instruction, and this requires the ability to address more than 2 data elements.
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skiboysteve - Friday, August 31, 2007 - link
this is stupid. they are adding SSE5 before SSE4. wow.tygrus - Friday, August 31, 2007 - link
SSE numbers/description becoming like model numbers. Confusing and virtually meaningless. Need CPU core with microcode to convert non-native SSE? instructions into sequence of native instuctions (micro-ops/macro-ops).If that doesn't happen then the compilers may need to re-write the code sequences for target(s) at compile time or execution.
yyrkoon - Thursday, August 30, 2007 - link
Just from what I have seen in the past, whenever AMD does something like this, Intel tries to seperate themselves by going a different direction, this is why I think Intel will rename their future instruction sets to something else.If AMD and Intel were to actually work together on this, then maybe Intel would opt in on some of the better portions of the instruction set that enhanced their CPUs, but somehow I do not think this is the case.
I watch the Intel/AMD 'rivalry' from the outside looking in, and I see the Coke/Pepsi 'war' all over again. Little kids going so far as to pull an engine out of a new delivery truck, paint it another color other than blue, because that *is* their rivals colors . . . At what cost for your share holders ? Nonesense !
jeromekwok - Thursday, August 30, 2007 - link
I don't think of a good reason we should care this SSE5A, or should we call it 3dnow technically. AMD may gain back a few benchmark scores, but it is hard to get developers move from Intel compiler suites.Do you guys feel the same. When the MADD goes thru the OOO, it should be decoded as MUL and ADD micro-ops. There should not be a big difference if we use two instructions MUL and ADD, which should get similar micro-ops. May be there is something AMD is weak at.
saratoga - Thursday, August 30, 2007 - link
Since muls have a very high latency compared to adds, and a dependency would exist between the ops, this would not be a good way to do things.
The result is the same (obviously), but its slower and complicates scheduling for no logical reason. Compared to a multiplier, adders are very cheap.
redpriest_ - Thursday, August 30, 2007 - link
Look at Itanium's fused multiply add.jiulemoigt - Thursday, August 30, 2007 - link
Well I wrote several versions but what it comes down to is I'm scratching my at the example as it looks like it was written by marketing without asking an engineer how to code it. The first can be written in half that many lines of code and more efficiently, it looks like vb code that was automatically translated by a very bad compiler. I've written code for both chips and generally hand coding will give code than four about four times faster but is not practical considering time constraints and the number of people that can write assembler code. Yet using instructions is supposed to speed up the rate code goes because the computer performs a series of instructions that have predefined procedures ie store data in A, store data in B, ADD A to B, repeat C times, return B, where as this looks like store data in A, store data in B, Add A,B store in C, return C, repeat with new numbers multiple times, go back and get data returned from C and store in A compare to data from pass two stored in B store result in C return C, get data just returned compare to data from pass three, store in C return C, get data just returned etc... with the second one using the location but still using a third location! Instead of ADD a,b with the result in B, return B to location 1, return B to loc2, then store loc 1 in A, loc 2 in B ADD A,B return B.The interesting thing about the number of instructions in the example is that the time it takes to one instruction to complete is far different, as store statements are not equal to compare statements are not equal to ADD/MUL statements, the computer can do an ADD statement faster than it can find data on local cache let alone system memory. One of the reason graphic cards are so much faster at MADD tends to do with the data being right there, which is why graphic DRR is so much more expensive than system memory. and now AMD wants to join the slowest instruction with the fast ones? This is something people should be really wondering about since it kills prefetch as it is going to make the system wait for data with every pass including the ones that should be really fast. That suggests they are going to try and force the scheduler to get longer blocks of data like Intel did with its P4 which was a very bad design since branching logic is only so good, and every miss will cause the CPU to sit ideal, covering up misses with longer cycles.
Any way for the non-coders SSE takes low level code and packages chunks of code that can be pasted to the CPU as one chunk it knows what to do with. Usually this makes the chunks get processed faster as scheduler on the CPU takes the chunks as one piece and it all gets pushed through no waiting, only in this case it is forcing the CPU to be an in-order CPU for every instruction so coded, which is bad because normally it can crank through fast instructions ideal through slow ones, this will force it to ideal through many slow ones, as opposed to simply burning through the fast short ones, less ideal time fast the job gets done, but with everything waiting on store statements there will be an increase in ideal time, since it is easier to stack a bunch of small legos in a box than four bowling balls. Just think of store statements as getting the legos or the bowling balls to put in the box you may have to make more trips to get enough legos to fill the box but the trips are faster and if you get two many legos the amount that does not fit will be small where as that last bowling balls is a significant amount compared to what is in the box. Rough analogy but I'm supposed to be relaxing not thinking about work.
Oh and MMX when it first came out was a PR stunt and it was only about two years after being added that someone found a use for it, as kludge to simply coding for people who were not willing to do it right. 3DNow was just as bad SSE was the first set that was actually useful, when added to compiler to speed up certain repetitive tasks like encoding and rendering. Though this new set defeats the purpose of having all those new registers to use!
PeteRoy - Thursday, August 30, 2007 - link
Return of the Jedi anyone?her34 - Thursday, August 30, 2007 - link
next for amd:the geforce 10800xt
peldor - Thursday, August 30, 2007 - link
This strikes me as a way to distract from the lack of a complete SSE4 implementation.