Project Larrabee

Intel describes project Larrabee as a “highly parallel, IA-based programmable architecture” that will be “easily programmable using many existing software tools, and designed to scale to trillions of floating point operations per second...” Intel goes on to say that “[the Larrabee architecture] will include enhancements to accelerate applications such as scientific computing, recognition, mining, synthesis, visualization, financial analytics and health applications.”

Intel would not say any more about project Larrabee, other than to confirm that it has begun planning products based around the architecture. Looking at the statements above, we can deduce one thing already.

Being based on IA, we expect Larrabee to implement some instance of the x86 ISA, but the real clue comes from the 3 TFLOPs performance target. Let’s get this straight: Larrabee is a super wide, FP powerhouse architecture that can do a better job at accelerating scientific computing applications than current Intel CPUs? Larrabee sure does sound a lot like a high end GPU.

Intel didn’t attach a timeframe to these Larrabee projects other than to say that they were in the initial planning stages now. It is highly unusual for Intel to come out and say that it is working on a very vague new architecture, we can only assume that there is some sort of political motivation behind the Larrabee disclosure.

Larrabee will be an important architecture to watch, we expect to hear more about it at this fall’s IDF back in the US.

More Vague Projects from Intel

Intel announced two other new projects that it’s working on, both of them less vague than the Larrabee announcement but still lacking in details. Pat Gelsinger unveiled Intel’s Tolapai project, a system on a chip (SoC) architecture for the enterprise market. The magic year for Tolapai is 2008, where Intel expects a high level of integration to reduce the footprint of the chip by up to 45% and power consumption by approximately 20% compared to “a standard four-chip design”. We can only assume that four chip design means CPU, North Bridge, South Bridge and Graphics. The 2008 introduction makes sense given that in 2008 Intel will introduce Nehalem which will offer configurations with integrated North Bridge and optional integrated graphics.

Intel will also be working on a SoC designed for the consumer electronics market in 2008, lending further credibility to many of AMD’s reasons for acquiring ATI. The real question is if Intel will be able to pull off market dominance in the CE market without acquiring an external graphics firm.

Final Words

We’re expecting more announcements out of Intel in the next two days, so stay tuned for continued coverage of IDF Beijing.

The Long Awaited Penryn Update
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  • rqle - Monday, April 16, 2007 - link

    My fear for AMD is that intel can clock their chip relatively higher and can ramp it up much faster than AMD. K10 will probably prove to be a stronger Quad chip clock for clock. But intel easy response is going to ramp up its Penryn chip up to 3.5+ range either matching or beating AMD chips and then KO? with its Nehalem onboard controller chip VERY shortly after the plan AMD launch.
  • fikimiki - Tuesday, April 17, 2007 - link

    You forget that every MHz means more power to consume. 3.5GHz chip will have 150W TDP or more. And 45nm won't help.
  • defter - Tuesday, April 17, 2007 - link

    Why wouldn't 45nm help? At 65nm, Intel will achieve 3GHz for quad core 130W TDP parts. It's quite logical to assume that Intel will hit at least 3.6GHz for quad core parts in Q1 2008 if necessary with 130W TDP naturally. That's only 20% clockspeed increase at the same TDP.

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